Zeke Wang (王则可)

Zeke Wang is a ZJU100 Young Professor at Zhejiang University in Computer Science.

Research Profile

His research interest is to use FPGAs to build systems for Machine Learning training, with a focus on the FPGA-enhanced computation and communication.

Computation: He proposes a one-size-fits-all framework (MLWeaving) that allows any-precision linear model training on FPGAs, as well as any-precision K-Means.

Communication: on-going. He believes the FPGA is a nice alternative platform for the communication needby by Machine Learning training. Keep updated...

Previously He has been working on programming FPGAs with high-level languages, with a focus on OpenCL.

Publications

2020

Shuhai: Benchmarking High Bandwidth Memory on FPGAs, Zeke Wang, Hongjing Huang, Jie Zhang, Gustavo Alonso, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020. [pdf][video]

StRoM: Smart Remote Memory, David Sidler, Zeke Wang, Monica Chiosa, Amit Kulkarni, Gustavo Alonso, European Conference on Computer Systems (EuroSys), 2020. [pdf]

Understanding and Optimizing ConjunctivePredicates under Memory-efficient Storage Layouts, Zeke Wang, Xue Liu, Kai Zhang, Haihang Zhou, Bingsheng He, IEEE Transactions on Knowledge and Data Engineering, 2020. [pdf]

BiS-KM: Enabling Any-Precision K-Means on FPGAs, Zhenhao He, Zeke Wang, Gustavo Alonso,ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2020. [pdf]

Boyi: A Systematic Framework for Automatically Deciding the Best Execution Model for OpenCL Applications on FPGAs, Jiantong Jiang, Zeke Wang, Xue Liu, Juan Gómez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2020.[pdf]

Tackling Hardware/Software Co-design from a Database Perspective, Gustavo Alonso, Timothy Roscoe, David Cock, Mohsen Ewaida, Kaan Kara, Dario Korolija, David Sidler, Zeke Wang, Conference on Innovative Data Systems Research (CIDR), 2020.[pdf]

2019

doppioDB 2.0: Hardware Techniques for Improved Integration of Machine Learning into Databases , Kaan Kara, Zeke Wang, Ce Zhang, Gustavo Alonso, International Conference on Very Large Data Bases (VLDB) Demo, 2019.[pdf]

Accelerating Generalized Linear Models with MLWeaving: A One-Size-Fits-All System for Any-Precision Learning, Zeke Wang, Kaan Kara, Hantian Zhang, Gustavo Alonso, Onur Mutlu, Ce Zhang, International Conference on Very Large Data Bases (VLDB), 2019.[pdf] [TR] [code]

DPI: The Data Processing Interface for Modern Networks, Gustavo Alonso, Carsten Binnig, Ippokratis Pandis, Kenneth Salem, Jan Skrzypczak, Ryan Stutsman, Lasse Thostrup, Tianzheng Wang, Zeke Wang, and Tobias Ziegler, Conference on Innovative Data Systems Research (CIDR), 2019.[pdf]

2018

Hebe: An Order-obliviousness and High-performance Execution Scheme for Conjunctive Predicates, Zeke Wang, Kai Zhang, Haihang Zhou, Xue Liu, Bingsheng He, IEEE International Conference on Data Engineering (ICDE), 2018. [pdf]

G-NET: Effective GPU Sharing in NFV Systems, Kai Zhang, Bingsheng He, Jiayu Hu, Zeke Wang, Bei Hua, Jiayi Meng, Lishan Yang, USENIX Symposium on Networked Systems Design and Implementation (NSDI), April, 2018.[pdf]

2017

Multi-kernel Data Partitioning with Channel on OpenCL-based FPGAs, Zeke Wang, Johns Paul, Bingsheng He, Wei Zhang, IEEE Trans. Very Large Scale Integr.(VLSI) System, 2017. [pdf]

2016

Relational Query Processing on OpenCL-based FPGAs, Zeke Wang, Johns Paul, HuiYan Cheah, Bingheng He, Wei Zhang , International Conference on Field Programmable Logic and Applications (FPL), Sep. 2016. [pdf]

A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs, Zeke Wang, Bingheng He, Wei Zhang, Shunning Jiang , 22nd IEEE Symposium on High Performance Computer Architecture (HPCA), Mar. 2016. [pdf]

Melia: A MapReduce Framework on OpenCL-based FPGAs, Zeke Wang, Shuhao Zhang, Bingsheng He, Wei Zhang , IEEE Trans. Parallel and Distributed System, 2016. [pdf]

Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application, Xue Liu, Zeke Wang, QingXu Deng, IEEE Trans. Very Large Scale Integr.(VLSI) System, Jan. 2016. [pdf]

2015

A study of data partitioning on OpenCL-based FPGAs , Zeke Wang, Bingheng He, Wei Zhang , 25th International Conference on Field Programmable Logic and Applications (FPL), Sep. 2015. [pdf]

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT, Zeke Wang, Xue Liu, Bingsheng He, Feng Yu , IEEE Trans. Very Large Scale Integr.(VLSI) System, 23(5), pp.973-977, Apr. 2015. [pdf]

2014 and before

Xue Liu, Q-X Deng, Zeke Wang, “Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers,” IEEE Transactions on Nuclear Science, 61(1), pp.561-567, Feb.2014.

Xue Liu, Qingxu Deng, Boning Hou, Zeke Wang, “High-speed, fixed-latency serial links with Xilinx FPGAs,” Journal of Zhejiang University SCIENCE C, 15(2), pp. 153-160, Feb.2014.

Zeke Wang, Feng Yu, Xue Liu, “Block Processor: A resource-distributed architecture,” IEEE High Performance Extreme Computing Conference (HPEC), Sep.2013.

Feng Yu, Ruifeng Ge, Zeke Wang, “Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors,” IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.7, pp. 1637-1641, Jul. 2013.

Xue Liu, Feng Yu, Zeke Wang, “A pipelined architecture for normal I/O order FFT,” J Zhejiang Univ-Sci C (Comput & Electron), 12(1), pp.76-82, 2011. Zhengguo Ma, Feng Yu, Ruifeng Ge, Zeke Wang, “An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays,” J Zhejiang Univ-Sci C (Comput & Electron), 12(4), pp.323-329 ,2011.

Feng Yu, Zeke Wang, Ruifeng Ge, “Novel algorithm for complex bit reversal: employing vector permutation and branch reduction methods,” J Zhejiang Univ-Sci A, 10(10), pp. 1492-1499, 2009.

Zeke Wang, HuiYan Cheah, Johns Paul, Bingheng He, Wei Zhang, “Accelerating Database Query Processing on OpenCL-based FPGAs,” 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2016. (poster)

Zeke Wang, Bingheng He, Wei Zhang, “Improving Data Partitioning Performance on OpenCL-Based FPGAs,” IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May. 2015. (poster)

Teaching

At UPM, Master Universitario en Software y Sistemas:

Performance Analysis and Modeling of Software Systems, Fall 2018 [website] [seminars@UPM]


In the past, at ETH Zurich:

Advanced Systems Lab, Fall 2017 [website]

Data Modelling and Databases, Spring 2017 [website]

Advanced Systems Lab, Fall 2016 (Head Teaching Assistant) [website]

Data Modelling and Databases, Spring 2016 [website]

Advanced Systems Lab, Fall 2015 [website]

Programmieren und Problemlösen, Spring 2015 [website]

Advanced Systems Lab, Fall 2014 [website]

Programmieren und Problemlösen, Spring 2014 [website]

Advanced Systems Lab, Fall 2013 [website]

Data Modeling and Databases, Spring 2012 [website]